We developed the application specific integrated circuit that connects to the Cadmium Telluride detector as described in the VIP module detector section. It reads out the deposited charge of every gamma photon interaction providing the energy and the time stamp of the hit. The architecture of the VIP-PIX ASIC is shown in Figure 1. It composes a 10 by 10 matrix of independent pixel front-end electronics separated by 1 millimeter, and back-end electronics with a digital controller, a time to digital converter, a temperature sensor, five voltage references, a current reference, and a 16-bit chip ID. The orientation of the pixels and the position of the digital and analog buses have been designed in such a way that digital interferences are minimized to the noise level. Moreover, to reduce the digital noise inside the ASIC during acquisition mode, every pixel has an individual differential clock line, which will just be enabled when the ADC is activated for digitization or just during the pixel data readout operation.
1. VIP-PIX Readout ASIC block diagram.
The ASIC is controlled by the following 8 digital signals: a 40 MHz clock; data in; data request; chip select; operation mode (3 bit); reset; digital test pulse; and TDC calibration pad. It provides two digital outputs: the trigger of the pixels; and the data out. Additionally an analog test pulse signal can be connected to the chip for quality control. It is biased with a single supply of 2.5 Volt and a 110 kOhm external resistor (REXT). The digital, analog, and mixed-signal VDD pads can be connected on board to a single supply with common decoupling capacitors connected close to the ASIC. The architecture of the smart pixel is presented in Figure 2. It is composed by an analog front-end, a 10-bit successive approximation register ADC, a set of configuration registers, and a digital controller with 4 operation modes. The analog front-end integrates a switchable-gain preamplifier with dynamic detector leakage current compensation circuit, a tunable CR-RC shaper, a double-polarity peak and hold circuit, and a discriminator with individual tunable threshold.
Figure 2. VIP-PIX smart pixel block diagram.
The measurement results of the VIP-PIX ASIC show an equivalent noise charge of 150 e- RMS, a minimum threshold of 1000 e-, a maximum jitter of 10ns for small energies up to 30 keV, and a jitter below 1ns for energies above 100 keV. The resolution of the time to digital converter is 600 ps. Due to the complexity of cooling down 6 millions pixels of the complete PET scanner, the ASIC was designed to work with a power consumption of just 200 micro-watts per pixel. Figure 3 shows a microphotography of the VIP-PIX ASIC. The size of the chip is 10.2 mm x 13 mm. A full engineering run of 12 wafers and mask production has been realized with TSMC foundry through the low volume production program from Europractice. It has been fabricated with 0.25 um CMOS Mixed-Signal process.
As proof of working conditions, a CdTe detector was bond-bonded to the VIP-PIX ASIC as shown in Figure 4 and a first spectroscopy measurements using Co-57 was realized. The spectroscopy plot is illustrated in Figure 5. A resolution of 4 % at full width half maximum was obtained with a 2-mm thick detector biased at -1000V at -10 Celsius degree. Eleven wafers with 189 VIP-PIX each are now being post-processed for further packaging steps toward the integration of the detector modules of VIP Project.
4. Photography of the VIP-PIX ASIC wafer.
5. Photography of the CdTe-VIP-PIX assembly.
6. First spectroscopy results of the VIP-PIX ASIC-CdTE assembly.